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LIS202DL
MEMS motion sensor 2-axis - 2g/8g smart digital output "piccolo" accelerometer
Feature

2.16V to 3.6V supply voltage 1.8V compatible IOs <1mW power consumption 2g/8g dynamically selectable Full-Scale I2C/SPI digital output interface Programmable interrupt generator Click and double click recognition Embedded high pass filter Embedded self test 10000g high shock survivability ECOPACK(R) RoHS and "Green" compliant (see Section 9) measuring accelerations with an output data rate of 100Hz or 400Hz. A self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate inertial wake-up interrupt signals when a programmable acceleration threshold is crossed at least in one of the two axes. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS202DL is available in plastic Thin Land Grid Array package (TLGA) and it is guaranteed to operate over an extended temperature range from -40C to +85C. The LIS202DL belongs to a family of products suitable for a variety of applications: - - - Motion activated functions Gaming and Virtual Reality input devices Vibration Monitoring and Compensation
LGA-14 (3x5x0.9mm)
Description
The LIS202DL is an ultra compact low-power two axes linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world through I2C/SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS202DL has dynamically user selectable full scales of 2g/8g and it is capable of Table 1. Device summary
Temp range, C -40 to +85 -40 to +85
Part number LIS202DL LIS202DLTR
Package LGA LGA
Packing Tray Tape and reel
June 2007
Rev 1
1/36
www.st.com 36
Contents
LIS202DL
Contents
1 Block diagram & pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1 2.4.2 2.4.3 2.4.4 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 5.2.2 5.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 7
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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LIS202DL
Contents
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 22 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1 8.2 8.3 Mechanical characteristics at 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mechanical Characteristics derived from measurement in the -40C to +85C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Electro-mechanical characteristics at 25C . . . . . . . . . . . . . . . . . . . . . . . 33
9 10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Block diagram & pin description
LIS202DL
1
1.1
Figure 1.
Block diagram & pin description
Block diagram
Block diagram
X+ Y+
CHARGE AMPLIFIER
MUX A/D CONVERTER CONTROL LOGIC
CS I2C SPI SCL/SPC SDA/SDO/SDI SDO
a
YX-
SELF TEST
REFERENCE
TRIMMING CIRCUITS
CLOCK
CONTROL LOGIC
&
INT 1 INT 2
INTERRUPT GEN.
1.2
Pin description
Figure 2. Pin connection
1
Y X
1
6
6 8
13
13
8
TOP VIEW
BOTTOM VIEW
Table 2.
Pin# 1 2 3 4 5 6
Pin description
Name Vdd_IO GND Reserved GND GND Vdd Power supply for I/O pins 0V supply Connect to Vdd 0V supply 0V supply Power supply Function
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LIS202DL Table 2.
Pin# 7 8 9 10 11 12
Block diagram & pin description Pin description (continued)
Name CS INT 1 INT 2 GND Reserved SDO SDA SDI SDO SCL SPC Function SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Inertial interrupt 1 Inertial interrupt 2 0V supply Connect to Gnd SPI Serial Data Output I2C less significant bit of the device address I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC)
13
14
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Mechanical and electrical specifications
LIS202DL
2
2.1
Mechanical and electrical specifications
Mechanical characteristics
(All the parameters are specified @ Vdd=2.5V, T = 25C unless otherwise noted)
Table 3.
Symbol FS
Mechanical characteristics(1)
Parameter Measurement range(3) Test conditions FS bit set to 0 FS bit set to 1 FS bit set to 0 Min. 2.0 8.0 16.2 64.8 Typ.(2) 2.3 9.2 18 72 0.01 40 60 0.5 19.8 mg/digit FS bit set to 1 79.2 %/C mg mg mg/C Max. Unit g
So
Sensitivity Sensitivity change vs temperature Typical zero-g level offset accuracy(4),(5) Zero-g level change vs temperature
TCSO
FS bit set to 0 FS bit set to 0 FS bit set to 1 Max delta from 25C FS bit set to 0 STP bit used X axis Vdd=2.16V to 3.6V FS bit set to 0 STP bit used Y axis Vdd=2.16V to 3.6V
TyOff
TCOff
-32
-3
LSb
Vst
Self test output change(6),(7),(8)
3
32
LSb
BW Top Wh
System bandwidth(9) Operating temperature range Product weight -40
ODR/2 +85 30
Hz C mgram
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V 2. Typical specifications are not guaranteed 3. Verified by wafer level test and measurement of initial offset and sensitivity 4. Typical zero-g level offset value after MSL3 preconditioning 5. Offset can be eliminated by enabling the built-in high pass filter 6. If STM bit is used values change in sign for all axes 7. Self Test output changes with the power supply. Self test "output change" is defined as OUTPUT[LSb](Self-test bit on ctrl_reg1=1) -OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=4.6g/256 at 8bit representation, 2.3g Full-Scale 8. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering 9. ODR is output data rate. Refer to table 3 for specifications
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LIS202DL
Mechanical and electrical specifications
2.2
Electrical characteristics
(All the parameters are specified @ Vdd=2.5V, T= 25C unless otherwise noted)
Table 4.
Symbol Vdd Vdd_IO Idd IddPdn VIH VIL VOH VOL
Electrical Characteristics(1)
Parameter Supply voltage I/O pins Supply voltage Supply current Current consumption in power-down mode Digital high level input voltage Digital low level input voltage High level output voltage Low level output voltage DR=0 100 Hz DR=1 400 ODR/2 3/ODR -40 +85 Hz s 0.9*Vdd _IO 0.1*Vdd _IO
(3)
Test conditions
Min. 2.16 1.71
Typ.(2) 2.5
Max. 3.6 Vdd+0.1
Unit V V mA A V
T = 25C, ODR=100Hz T = 25C 0.8*Vdd _IO
0.3 1
0.4 5
0.2*Vdd _IO
V V V
ODR BW Ton Top
Output data rate System bandwidth(4) Turn-on time
(5)
Operating temperature range
C
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V 2. Typical specification are not guaranteed 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Filter cut-off frequency 5. Time to obtain valid data after exiting Power-Down mode
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Mechanical and electrical specifications
LIS202DL
2.3
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol Vdd Vdd_IO Vin Supply voltage I/O pins supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO) Acceleration (any axis, powered, Vdd=2.5V) 10000g for 0.1 ms 3000g for 0.5 ms AUNP TOP TSTG Acceleration (any axis, unpowered) 10000g for 0.1 ms Operating temperature range Storage temperature range -40 to +85 -40 to +125 4.0 (HBM) ESD Electrostatic discharge protection 200 (MM) 1500 (CDM) C C kV V V
Absolute maximum ratings
Ratings Maximum Value -0.3 to 6 -0.3 to 6 -0.3 to Vdd_IO +0.3 3000g for 0.5 ms Unit V V V
APOW
Note:
Supply voltage on any pin should never exceed 6.0V
This is a Mechanical Shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part
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LIS202DL
Mechanical and electrical specifications
2.4
2.4.1
Terminology
Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, 1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensors.
2.4.2
Zero-g level
Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see "Zero-g level change vs. temperature". The Zero-g level tolerance (TyOff) describes the Standard Deviation of the range of Zero-g levels of a population of sensors.
2.4.3
Self test
Self Test allows to check the sensor functionality without moving it. The Self Test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to `0`. When the selftest bit of ctrl_reg1 is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebric sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
2.4.4
Click and double click recognition
The click and double click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction. If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pins (INT1 and/or INT2). A more advanced feature allows to generate an interrupt request when a "double click" stimulus is applied. A programmable time between the two events allows a flexible adoption to the application requirements. Mouse-button like application like clicks and double clicks can be implemented. This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli.
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Functionality
LIS202DL
3
Functionality
The LIS202DL is an ultracompact, low-power, digital output 2-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface.
3.1
Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in pF range.
3.2
IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by analog-to-digital converters. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS202DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS202DL may also be configured to generate an inertial Wake-Up interrupt signal accordingly to a programmed acceleration event along the enabled axes.
3.3
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows to use the device without further calibration.
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LIS202DL
Application hints
4
Application hints
Figure 3. LIS202DL electrical connection
Vdd Vdd_IO
6
1
1
Y X
10uF
Top VIEW
6 8
13
100nF
8
13
TOP VIEW
SDA/SDI/SDO
DIRECTION OF THE DETECTABLE ACCELERATIONS
SCL/SPC
INT_1
INT_2
GND
Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be placed as near as possible to the pin 6 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (Figure 3: LIS202DL electrical connection). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the I2C/SPI interface.When using the I2C, CS must be tied high while SDO must be left floating. The functions, the threshold an the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the I2C/SPI interface.
4.1
Soldering information
The LGA package is compliant with the ECOPACK, RoHS and "green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Pin #1 indicator is electrically connected to pin 1. Leave pin 1 indicator unconnected during soldering. Land pattern and soldering recommendation are available at www.st.com/mems.
SDO
CS
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Digital interfaces
LIS202DL
5
Digital interfaces
The registers embedded inside the LIS202DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 6. Serial interface pin description
PIn description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO)
PIn name CS SCL/SPC
SDA/SDI/SDO SDO
5.1
I2C serial interface
The LIS202DL I2C is a bus slave. The I2C is employed to write the data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 7.
Term Transmitter Receiver Master Slave
Serial interface pin description
Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS202DL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as the normal mode.
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LIS202DL
Digital interfaces
5.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The Slave ADdress (SAD) associated to the LIS202DL is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is `1' (address 0011101b) else if SDO pad is connected to ground LSb value is `0' (address 0011100b). This solution permits to connect and address two different accelerometer to the same I2C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I2C embedded inside the LIS202DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically increment to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged.
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Digital interfaces
LIS202DL
Transfer when Master is writing one byte to slave:
Master Slave ST SAD + W SAK SUB SAK DATA SAK SP
Transfer when Master is writing multiple bytes to slave:
Master Slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP
Transfer when Master is receiving (reading) one byte of data from slave:
Master Slave ST SAD+W SAK SUB SAK SR SAD+R SAK DATA NMAK SP
Transfer when Master is receiving (reading) multiple bytes of data from slave:
Master Slave ST SAD + W SAK SUB SAK SR SAD + R SAK DATA MAK
Master Slave DATA
MAK DATA
NMAK
SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.
5.2
SPI bus interface
The LIS202DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
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LIS202DL Figure 4.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
Digital interfaces Read & write protocol
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
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Digital interfaces
LIS202DL
5.2.1
SPI read
Figure 5. SPI read protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 6.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
Multiple bytes SPI read protocol (2 bytes example)
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
5.2.2
SPI write
Figure 7.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SPI write protocol
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LIS202DL
Digital interfaces The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 8.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
Multiple bytes SPI write protocol (2 bytes example)
5.2.3
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 9.
CS SPC SDI/O
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SPI read protocoin 3-wires model
The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode.
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Register mapping
LIS202DL
6
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 8. Register address map
Register address Name Reserved (do not modify) Who_Am_I Reserved (do not modify) Ctrl_Reg1 Ctrl_Reg2 Ctrl_Reg3 HP_filter_reset Reserved (do not modify) Status_Reg -OutX -OutY --Reserved (do not modify) WU_CFG_1 WU_SRC_1(ack1) WU_THS_1 WU_DURATION_1 WU_CFG_2 WU_SRC_2 (ack2) WU_THS_2 WU_DURATION_2 CLICK_CFG CLICK_SRC (ack) -CLICK_THSY_X -rw rw rw r rw rw rw r rw rw rw r r r r r r r r rw rw rw r r Type Hex 00-0E 0F 10-1F 20 21 22 23 24-26 27 28 29 2A 2B 2C 2D 2E-2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 011 1011 00000000 011 1100 00000000 Not used 011 0000 00000000 011 0001 00000000 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 011 1000 00000000 011 1001 00000000 Not used 010 0111 00000000 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 output Not used Not used Reserved output Not used Not used 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 dummy Dummy register Reserved 000 1111 00111011 Binary Reserved Dummy register Reserved Default Comment
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LIS202DL Table 8. Register address map
Register address Name CLICK_TimeLimit CLICK_Latency CLICK_Window Type Hex rw rw rw 3D 3E 3F Binary 011 1101 00000000 011 1110 00000000 011 1111 00000000 Default
Register mapping
Comment
Registers marked as reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
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Register description
LIS202DL
7
Register description
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.
7.1
WHO_AM_I (0Fh)
Table 9.
0
Register
0 1 1 1 0 1 1
Device identification register. This register contains the device identifier that for LIS202DL is set to 3Bh.
7.2
CTRL_REG1 (20h)
Table 10.
DR
Register
PD FS STP STM 0(1) Yen Xen
1. Bit to be set to "0" for correct device functionality
Table 11.
DR PD FS STP, STM Yen Xen
Register description
Data rate selection. Default value: 0 (0: 100 Hz output data rate; 1: 400 Hz output data rate) Power Down Control. Default value: 0 (0: power down mode; 1: active mode) Full scale selection. Default value: 0 (refer to Table 2 for typical full scale value) Self Test Enable. Default value: 00 (0: normal mode; 1: self test P, M enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled)
DR bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100Hz. By changing the content of DR to "1" the selected data-rate will be set equal to 400Hz. PD bit allows to turn on the turn the device out of power-down mode. The device is in powerdown mode when PD= "0" (default value after boot). The device is in normal mode when PD is set to 1.
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LIS202DL
Register description STP, STM bits are used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to Table 3 and Table 4 for specification) thus allowing to check the functionality of the whole measurement chain. Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1. The default value is 1.
7.3
CTRL_REG2 (21h)
Table 12.
SIM
Register
BOOT -FDS HP WU2 HP WU1 HP_coeff2 HP_coeff1
Table 13.
SIM BOOT FDS HP WU2 HP WU1 HP coeff2 HP coeff1
Register description
SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) High Pass filter enabled for WakeUp # 2. Default value: 0 (0: filter bypassed; 1: filter enabled) High Pass filter enabled for Wake-Up #1. Default value: 0 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 (See table below)
SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad. BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft.
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Register description
LIS202DL
Table 14.
Truth table
ft (Hz) (ODR=100 Hz) 2 1 0.5 0.25 ft (Hz) (ODR=400 Hz) 8 4 2 1
HPcoeff2,1 00 01 10 11
7.4
CTRL_REG3 [Interrupt CTRL register] (22h)
Table 15.
IHL
Register
PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0
Table 16.
IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0
Register description
Interrupt active high, low. Default value 0. (0: active high; 1: active low) Push-pull/Open Drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Data Signal on Int2 pad control bits. Default value 000. (see table below) Data Signal on Int1 pad control bits. Default value 000. (see table below)
Table 17.
Truth table
I1(2)_CFG1 0 0 1 1 0 1 I1(2)_CFG0 0 1 0 1 0 1 Int1(2) Pad GND WU_1 WU_2 WU_1 or WU_2 Data Ready Click Interrupt
I1(2)_CFG2 0 0 0 0 1 1
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LIS202DL
Register description
7.5
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all two axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.
7.6
STATUS_REG (27h)
Table 18.
XYOR
Register
-YOR XOR YXDA -YDA XDA
Table 19.
YXOR
Register description
X, Y axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: new data has over written the previous one before it was read) Y axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) X, Y axis new Data Available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Y axis new Data Available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) X axis new Data Available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
YOR
XOR
YXDA YDA
XDA
7.7
OUT_X (29h)
Table 20.
XD7
Register
XD6 XD5 XD4 XD3 XD2 XD1 XD0
X axis output data.
7.8
OUT_Y (2Bh)
Table 21.
YD7
Register
YD6 YD5 YD4 YD3 YD2 YD1 YD0
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Register description Y axis output data.
LIS202DL
7.9
WU_CFG_1 (30h)
Table 22.
AOI
Register
LIR res_1 res_2 YHIE YLIE XHIE XLIE
Table 23.
AOI
Register description
And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into WU_SRC_1 reg with the WU_SRC_1 reg cleared by reading WU_SRC_1 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Reserved at Value: 0. Value should not be changed. Reserved at Value: 0. Value should not be changed. Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
LIR res_1 res_2 YHIE
YLIE
XHIE
XLIE
7.10
WU_SRC_1 (31h)
Table 24.
--
Register
IA --YH YL XH XL
Table 25.
IA YH YL
Register description
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Y High. Default value: 0 (0: no interrupt, 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt, 1: YL event has occurred)
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LIS202DL Table 25.
XH XL
Register description Register description
X High. Default value: 0 (0: no interrupt, 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt, 1: XL event has occurred)
Wake-up source register. Read only register. Reading at this address clears WU_SRC_1 register and the WU 1 interrupt and allows the refreshment of data in the SRC_1 register if the latched option was chosen.
7.11
WU_THS_1 (32h)
Table 26.
DCRM
Register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 27.
DCRM
Register description
Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decremented) Wake-up Threshold: default value: 000 0000
THS6, THS0
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented.
7.12
WU_DURATION_1 (33h)
Table 28.
D7
Register
D6 D5 D4 D3 D2 D1 D0
Table 29.
D7-D0
Register description
Duration value. Default value: 0000 0000
Duration register for Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified
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Register description
LIS202DL
7.13
WU_CFG_2 (34h)
Table 30.
AOI
Register
LIR res_1 res_2 YHIE YLIE XHIE XLIE
Table 31.
AOI LIR
Register description
And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into WU_SRC_2 reg with the WU_SRC_2 reg cleared by reading WU_SRC_2 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Reserved at Value: 0. Value should not be changed. Reserved at Value: 0. Value should not be changed. Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
res_1 res_2 YHIE
YLIE
XHIE
XLIE
7.14
WU_SRC_2 (35h)
Table 32.
--
Register
IA --YH YL XH XL
Table 33.
IA
Register description
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated)
YH YL
Y High. Default value: 0 (0: no interrupt; 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: YL event has occurred)
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LIS202DL Table 33. XH XL Register description X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred)
Register description
Wake-up source register. Read only register. Reading at this address clears WU_SRC_2 register and the WU_2 interrupt and allows the refreshment of data in the WU_SRC_2 register if the latched option was chosen.
7.15
WU_THS_2 (36h)
Table 34.
DCRM
Register
THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 35.
DCRM THS6, THS0
Register description
Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decrements) Wake-up Threshold. Default value: 000 0000
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented.
7.16
WU_DURATION_2 (37h)
Table 36.
D7
Register
D6 D5 D4 D3 D2 D1 D0
Table 37. D7-D0
Register description Duration value. Default value: 0000 0000
Duration register for Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified.
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Register description
LIS202DL
7.17
CLICK_CFG (38h)
Table 38.
LIR res_1 res_2 Double_Y Single_Y Double_X Single_X
Table 39. LIR
Register description
Latch Interrupt request into CLICK_SRC reg with the CLICK_SRC reg refreshed by reading CLICK_SRC reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
res_1 res_2 Reserved at Value: 0. Value should not be changed. Reserved at Value: 0. Value should not be changed. Enable interrupt generation on double click event on Y axis. Default value: 0
Double_Y Single_Y Double_X Single_X
(0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on single click event on Y axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on double click event on X axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on single click event on X axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Table 40.
Truth table
Single_Y / X 0 1 0 1 0 Single Double Single or Double Click output
Double_Y / X 0 0 1 1
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LIS202DL
Register description
7.18
CLICK_SRC (39h)
Table 41.
--
Register
IA --Double_Y Single_Y Double_X Single_X
Table 42.
IA
Register description
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Double click on Y axis event. Default value: 0 (0: no interrupt; 1: Double Y event has occurred) Single click on Y axis event.Default value: 0 (0: no interrupt; 1: Single Y event has occurred) Double click on X axis event. Default value: 0 (0: no interrupt; 1: Double X event has occurred) Single click on X axis event. Default value: 0 (0: no interrupt; 1: Single X event has occurred)
Double_Y Single_Y Double_X Single_X
7.19
CLICK_THSY_X (3Bh)
Table 43.
THSy3
Register
THSy2 THSy1 THSy0 THSx3 THSx2 THSx1 THSx0
Table 44.
Register description
THSy3, THSy0 Click Threshold on Y axis. Default value: 0000 THSx3, THSx0 Click Threshold on X axis. Default value: 0000
From 0.5g(0001) to 7.5g(1111) with step of 0.5g.
7.20
CLICK_TimeLimit (3Dh)
Table 45.
Dur7
Register
Dur6 Dur5 Dur4 Dur3 Dur2 Dur1 Dur0
From 0 to 127.5msec with step of 0.5 msec.
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Register description
LIS202DL
7.21
CLICK_Latency (3Eh)
Table 46.
Lat7
Register
Lat6 Lat5 Lat4 Lat3 Lat2 Lat1 Lat0
From 0 to 255 msec with step of 1 msec.
7.22
CLICK_Window (3Fh)
Table 47.
Win7
Register
Win6 Win5 Win4 Win3 Win2 Win1 Win0
From 0 to 255 msec with step of 1 msec.
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LIS202DL
Typical performance characteristics
8
8.1
Typical performance characteristics
Mechanical characteristics at 25C
Figure 11. X axis sensitivity at 2.5V
Figure 10. X axis 0-g level at 2.5V
25
20 18
20 Percent of parts (%)
Percent of parts (%)
16 14 12 10 8 6 4 2
15
10
5
0 -200
-150
-100
-50 0 50 0-g LEVEL (mg)
100
150
200
0 16
16.5
17
17.5 18 18.5 sensitivity (mg/digit)
19
19.5
20
Figure 12. Y axis 0-g level at 2.5V
Figure 13. Y axis sensitivity at 2.5V
35 30 25 20 15 10 5 0 -200
20 18 16
Percent of parts (%)
Percent of parts (%)
14 12 10 8 6 4 2
-150
-100
-50 0 50 0-g LEVEL (mg)
100
150
200
0 16
16.5
17
17.5 18 18.5 sensitivity (mg/digit)
19
19.5
20
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Typical performance characteristics
LIS202DL
8.2
Mechanical Characteristics derived from measurement in the -40C to +85C temperature range
Figure 15. X axis sensitivity change vs. temperature at 2.5V
60
Figure 14. X axis 0-g level change vs. temperature at 2.5V
35 30 25 20 15 10 5 0 -3
50 Percent of parts (%)
Percent of parts (%)
40
30
20
10
-2
-1 0 1 0-g level drift (mg/C)
2
3
0 -0.05
0 sensitivity drift (%/deg. C)
0.05
Figure 16. Y axis 0-g level change vs. temperature at 2.5V
35 30 25 20 15 10 5 0 -3
Figure 17. Y axis sensitivity change vs. temperature at 2.5V
60
50 Percent of parts (%) -2 -1 0 1 0-g level drift (mg/C) 2 3
Percent of parts (%)
40
30
20
10
0 -0.05
0 sensitivity drift (%/deg. C)
0.05
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LIS202DL
Typical performance characteristics
8.3
Electro-mechanical characteristics at 25C
Figure 19. Current consumption in power down mode at 2.5V
35 30 25 20 15 10 5 0 -1
Figure 18. Current consumption in normal mode at 2.5V
35 30 25 20 15 10 5 0 200
250
300 350 current consumption (uA)
400
Percent of parts (%)
Percent of parts (%)
0
1 2 3 current consumption (uA)
4
5
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Package information
LIS202DL
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 20. LGA 14: mechanical data & package dimensions
mm DIM. MIN. A1 A2 A3 D1 E1 e d L1 N N1 P1 P2 T1 T2 R h k i s 0.965 0.640 0.750 0.450 1.200 0.150 0.050 0.100 0.100 0.180 2.850 4.850 0.220 3.000 5.000 0.800 0.300 4.000 1.360 1.200 0.975 0.650 0.800 0.500 TYP. 0.920 MAX. 1.000 0.700 MIN. TYP. MAX. 0.0362 0.0394 0.0275 inch
OUTLINE AND MECHANICAL DATA
0.260 0.0071 0.0087 0.0102 3.150 0.1122 0.1181 0.1240 5.150 0.1909 0.1968 0.2027 0.0315 0.0118 0.1575 0.0535 0.0472 0.985 0.0380 0.0384 0.0386 0.660 0.0252 0.0256 0.0260 0.850 0.0295 0.0315 0.0335 0.550 0.0177 0.0197 0.0217 1.600 0.0472 0.0059 0.0020 0.0039 0.0039 0.0630
LGA14 (3x5x0.92mm) Pitch 0.8mm Land Grid Array Package
7773587 C
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LIS202DL
Revision history
10
Revision history
Table 48.
Date 11-Jun-2007
Document revision history
Revision 1 Initial release. Changes
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LIS202DL
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